The present invention relates to a circuit for generating a reference voltage in a memory device. More particularly, the present invention relates to a circuit for generating a reference voltage optimized for a surrounding temperature.
It is important to maintain a stable internal operation voltage in a semiconductor memory device so as to ensure operation stability and reliability of the semiconductor memory device.
Specially, even though an outside power supply voltage is changed, the changed outside power supply voltage should not affect the internal voltage of the semiconductor memory device. Hence, a circuit for generating a reference voltage having a constant voltage level is required for stably operating the semiconductor memory device.
Recently, as the semiconductor memory device shrinks there has been a need for a circuit for supplying a low power supply voltage. Accordingly, the circuit for generating the reference voltage is required even more in this semiconductor memory device.
The reference voltage outputted from the circuit for generating the reference voltage will vary in accordance with a change in the power supply voltage inputted from an outside apparatus (not shown), the process of manufacturing the semiconductor memory device and a change in temperature. That is, the reference voltage has high deviation in accordance with the change and the process.
FIG. 1 is a view illustrating a threshold voltage distribution of a memory cell at two temperatures in a common semiconductor memory device.
FIG. 1 shows the threshold voltage distribution of the memory cell in accordance with a program state of the memory cell. Here, the threshold voltage distribution has a state 1 and a state 2.
In the state 1, data is read by using a first read voltage Vread1, and a verifying operation for a program data is performed by using a first verifying voltage Vverify1. In addition, in the state 2, data is read by using a second read voltage Vread2, and a verifying operation for a program data is performed by using a second verifying voltage Vverify2. Here, the read voltages Vread1 and Vread2, and the verifying voltages Vverify1 and Vverify2 are applied to a word line when the data in the memory cell are read or verified. These voltages Vread1, Vread2, Vverify1 and Vverify2 are generated on the basis of the reference voltage so that the voltages Vread1, Vread2, Vverify1 and Vverify2 should not be changed in accordance with PVT (process, voltage and temperature).
However, since the memory cell in the memory device has the characteristic of an N-MOS transistor, the threshold voltage of the memory cell is changed depending on the temperature.
In other words, the threshold voltage of the memory cell is decreased as the temperature is increased. As a result, a cell distribution of the memory cell is changed as shown in FIG. 1 in accordance with the temperature.
Accordingly, the memory cell has the cell distribution shown in a solid line of FIG. 1 when the temperature is high. However, the cell distribution of the memory cell is changed as shown in a dotted line of FIG. 1 when the temperature is low.
As mentioned above, the circuit for generating the reference voltage is set to generate the reference voltage having a constant value irrespective of the PVT. However, the circuit does not take into consideration the threshold voltage change of the memory cell in accordance with the temperature. Hence, a read or program error may occur in the memory cell.